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This commit is contained in:
Philippe Teuwen
2020-05-21 15:06:17 +02:00
parent f52d04e0a7
commit 4525cd1c32
9 changed files with 455 additions and 470 deletions
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130
libnfc/chips/pn53x.c
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@@ -580,8 +580,8 @@ pn53x_decode_target_data(const uint8_t *pbtRawData, size_t szRawData, pn53x_type
case NMT_ISO14443BICLASS:
// Store the UID
for(uint8_t i= 0 ; i < 8 ; ++i)
pnti->nhi.abtUID[7 - i]= pbtRawData[i];
for (uint8_t i = 0 ; i < 8 ; ++i)
pnti->nhi.abtUID[7 - i] = pbtRawData[i];
break;
case NMT_ISO14443B2CT:
@@ -1060,51 +1060,51 @@ pn53x_initiator_init(struct nfc_device *pnd)
// iclass requires special modulation settings
void pn53x_initiator_init_iclass_modulation(struct nfc_device *pnd)
{
// send a bunch of low level commands reverse engineered from a working iClass reader
// original device was using a PN512
//
// // TxModeReg - Defines the data rate and framing during transmission.
//// set bit 4 for target mode? - RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field is detected in Target mode for NFCIP-1 or in Card Communication mode
//pn512_write_register(0x12, "\x03", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_TxMode, 0x03);
//
// // RxModeReg - Defines the data rate and framing during reception.
//pn512_write_register(0x13, "\x03", 1, false);
// addy changed to set bit 3 - RxNoErr (put data in fifo before flagging read end)
//pn512_write_register(0x13, "\x0B", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_RxMode, 0x0B);
// send a bunch of low level commands reverse engineered from a working iClass reader
// original device was using a PN512
//
// // TxModeReg - Defines the data rate and framing during transmission.
//// set bit 4 for target mode? - RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field is detected in Target mode for NFCIP-1 or in Card Communication mode
//pn512_write_register(0x12, "\x03", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_TxMode, 0x03);
//
// // RxModeReg - Defines the data rate and framing during reception.
//pn512_write_register(0x13, "\x03", 1, false);
// addy changed to set bit 3 - RxNoErr (put data in fifo before flagging read end)
//pn512_write_register(0x13, "\x0B", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_RxMode, 0x0B);
// ManualRCVReg - Allows manual fine tuning of the internal receiver.
//pn512_write_register(0x1d, "\x10", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_ManualRCV, 0x10);
// ManualRCVReg - Allows manual fine tuning of the internal receiver.
//pn512_write_register(0x1d, "\x10", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_ManualRCV, 0x10);
// RFCfgReg - Configures the receiver gain and RF level detector sensitivity.
//pn512_write_register(0x26, "\x70", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_RFCfg, 0x70);
// RFCfgReg - Configures the receiver gain and RF level detector sensitivity.
//pn512_write_register(0x26, "\x70", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_RFCfg, 0x70);
// GsNOffReg - Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off.
//pn512_write_register(0x23, "\x88", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_GsNOFF, 0x88);
// GsNOffReg - Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off.
//pn512_write_register(0x23, "\x88", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_GsNOFF, 0x88);
// GsNOnReg - Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on.
//pn512_write_register(0x27, "\xf8", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_GsNOn, 0xf8);
// GsNOnReg - Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on.
//pn512_write_register(0x27, "\xf8", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_GsNOn, 0xf8);
// CWGsPReg - Defines the conductance of the P-driver during times of no modulation.
//pn512_write_register(0x28, "\x3f", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_CWGsP, 0x3f);
// CWGsPReg - Defines the conductance of the P-driver during times of no modulation.
//pn512_write_register(0x28, "\x3f", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_CWGsP, 0x3f);
// ModGsPReg - Defines the driver P-output conductance during modulation.
//pn512_write_register(0x29, "\x10", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_ModGsP, 0x10);
// ModGsPReg - Defines the driver P-output conductance during modulation.
//pn512_write_register(0x29, "\x10", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_ModGsP, 0x10);
// TReloadReg (MSB) - Describes the MSB of the 16-bit long timer reload value.
//pn512_write_register(0x2c, "\x69", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_TReloadVal_hi, 0x69);
// TReloadReg (MSB) - Describes the MSB of the 16-bit long timer reload value.
//pn512_write_register(0x2c, "\x69", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_TReloadVal_hi, 0x69);
// TReloadReg (LSB) - Describes the LSB of the 16-bit long timer reload value.
//pn512_write_register(0x2d, "\xf0", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_TReloadVal_lo, 0xf0);
// TReloadReg (LSB) - Describes the LSB of the 16-bit long timer reload value.
//pn512_write_register(0x2d, "\xf0", 1, false);
pn53x_WriteRegister(pnd, PN53X_REG_CIU_TReloadVal_lo, 0xf0);
}
int
@@ -1202,10 +1202,10 @@ pn53x_initiator_select_passive_target_ext(struct nfc_device *pnd,
}
szTargetsData = 6; // u16 UID_LSB, u8 prod code, u8 fab code, u16 UID_MSB
} else if (nm.nmt == NMT_ISO14443BICLASS) {
pn53x_initiator_init_iclass_modulation(pnd);
//
pn53x_initiator_init_iclass_modulation(pnd);
//
// Some work to do before getting the UID...
// send ICLASS_ACTIVATE_ALL command - will get timeout as we don't expect response
// send ICLASS_ACTIVATE_ALL command - will get timeout as we don't expect response
uint8_t abtReqt[] = { 0x0a }; // iClass ACTIVATE_ALL
uint8_t abtAnticol[11];
if ((res = pn53x_initiator_transceive_bytes(pnd, abtReqt, sizeof(abtReqt), NULL, 0, timeout)) < 0) {
@@ -1214,35 +1214,35 @@ pn53x_initiator_select_passive_target_ext(struct nfc_device *pnd,
// continue;
//} else
// return res;
}
// do select - returned anticol contains 'handle' for tag if present
abtReqt[0]= 0x0c; // iClass SELECT
abtAnticol[0]= 0x81; // iClass ANTICOL
}
// do select - returned anticol contains 'handle' for tag if present
abtReqt[0] = 0x0c; // iClass SELECT
abtAnticol[0] = 0x81; // iClass ANTICOL
if ((res = pn53x_initiator_transceive_bytes(pnd, abtReqt, sizeof(abtReqt), &abtAnticol[1], sizeof(abtAnticol) - 1, timeout)) < 0) {
log_put(LOG_GROUP, LOG_CATEGORY, NFC_LOG_PRIORITY_DEBUG, "timeout on iClass anticol");
return res;
}
// write back anticol handle to get UID
}
// write back anticol handle to get UID
if ((res = pn53x_initiator_transceive_bytes(pnd, abtAnticol, 9, abtTargetsData, 10, timeout)) < 0) {
log_put(LOG_GROUP, LOG_CATEGORY, NFC_LOG_PRIORITY_DEBUG, "timeout on iClass get UID");
return res;
}
}
log_put(LOG_GROUP, LOG_CATEGORY, NFC_LOG_PRIORITY_DEBUG, "iClass raw UID: %02x %02x %02x %02x %02x %02x %02x %02x", abtTargetsData[0], abtTargetsData[1], abtTargetsData[2], abtTargetsData[3], abtTargetsData[4], abtTargetsData[5], abtTargetsData[6], abtTargetsData[7]);
szTargetsData = 8;
nttmp.nm = nm;
if ((res = pn53x_decode_target_data(abtTargetsData, szTargetsData, CHIP_DATA(pnd)->type, nm.nmt, &(nttmp.nti))) < 0) {
return res;
}
} else {
if ((res = pn53x_initiator_transceive_bytes(pnd, pbtInitData, szInitData, abtTargetsData, sizeof(abtTargetsData), timeout)) < 0) {
if ((res == NFC_ERFTRANS) && (CHIP_DATA(pnd)->last_status_byte == 0x01)) { // Chip timeout
continue;
} else
szTargetsData = 8;
nttmp.nm = nm;
if ((res = pn53x_decode_target_data(abtTargetsData, szTargetsData, CHIP_DATA(pnd)->type, nm.nmt, &(nttmp.nti))) < 0) {
return res;
}
} else {
if ((res = pn53x_initiator_transceive_bytes(pnd, pbtInitData, szInitData, abtTargetsData, sizeof(abtTargetsData), timeout)) < 0) {
if ((res == NFC_ERFTRANS) && (CHIP_DATA(pnd)->last_status_byte == 0x01)) { // Chip timeout
continue;
} else
return res;
}
szTargetsData = (size_t)res;
}
szTargetsData = (size_t)res;
}
nttmp.nm = nm;
if ((res = pn53x_decode_target_data(abtTargetsData, szTargetsData, CHIP_DATA(pnd)->type, nm.nmt, &(nttmp.nti))) < 0) {
@@ -2249,7 +2249,7 @@ static int pn53x_ISO14443B_SR_is_present(struct nfc_device *pnd)
static int pn53x_ISO14443B_ICLASS_is_present(struct nfc_device *pnd)
{
int timeout= 300;
int timeout = 300;
log_put(LOG_GROUP, LOG_CATEGORY, NFC_LOG_PRIORITY_DEBUG, "%s", "target_is_present(): Ping B iClass");
pn53x_initiator_init_iclass_modulation(pnd);
//
@@ -2261,8 +2261,8 @@ static int pn53x_ISO14443B_ICLASS_is_present(struct nfc_device *pnd)
log_put(LOG_GROUP, LOG_CATEGORY, NFC_LOG_PRIORITY_DEBUG, "got expected timeout on iClass activate all");
}
// do select - returned anticol contains 'handle' for tag if present
abtReqt[0]= 0x0c; // iClass SELECT
abtAnticol[0]= 0x81; // iClass ANTICOL
abtReqt[0] = 0x0c; // iClass SELECT
abtAnticol[0] = 0x81; // iClass ANTICOL
if (pn53x_initiator_transceive_bytes(pnd, abtReqt, sizeof(abtReqt), &abtAnticol[1], sizeof(abtAnticol) - 1, timeout) < 0) {
log_put(LOG_GROUP, LOG_CATEGORY, NFC_LOG_PRIORITY_DEBUG, "timeout on iClass anticol");
return NFC_ETGRELEASED;;